디지털 시스템설계
- 한경국립대학교
- 김수찬
페이스북
트위터
카카오톡
네이버밴드
링크복사
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- 주제분류
- 공학 >컴퓨터ㆍ통신 >정보통신공학
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- 강의학기
- 2012년 2학기
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- 조회수
- 5,825
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1. Represent gates and combinational logic by concurrent VHDL statements.
2. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals
3. Given the present state and desired next state of F/F, determine the required F/F/ inputs.
4. Analyze a sequential circuit by signal tracing.
5. Given a problem statement for the design of a Mealy or Moore sequential circuit, find the corresponding state graph and table.
6. Specify a suitable set of state assignments for a state table, eliminating those assignments which are equivalent with respect to the cost of realizing the circuit
7. Design a sequential circuit using gates and flip-flops.
2. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals
3. Given the present state and desired next state of F/F, determine the required F/F/ inputs.
4. Analyze a sequential circuit by signal tracing.
5. Given a problem statement for the design of a Mealy or Moore sequential circuit, find the corresponding state graph and table.
6. Specify a suitable set of state assignments for a state table, eliminating those assignments which are equivalent with respect to the cost of realizing the circuit
7. Design a sequential circuit using gates and flip-flops.
차시별 강의
| 1. | |
instruction to VHDL (1/2) | 1. VHDL Description of Combinational Circuits 2. VHDL Models for Multiplexers 3. VHDL Modules |  |
| 2. | |
instruction to VHDL (2/2) | 1. Signals and Constants/ Arrays 2. VHDL Operators/ Packages and Libraries 3. IEEE Standard Logic/ Compilation and Simulation of VHDL Code | |
| 3. | |
Latches and Flip-Flops (1/2) | 1. Introduction 2. Set-Reset Latch 3. Gated D Latch | |
| 4. | |
Latches and Flip-Flops (2/2) | 1. Edge-Triggered D Flip-Flop/ S-R Flip-Flop 2. J-K Flip-Flop/ T Flip-Flop 3. Flip-Flop with Additional Inputs/ Summary | |
| 5. | |
Registers and Counter (1/2) | 1. Registers and Register Transfers 2. Shift Registers 3. Design of Binary Counters | |
| 6. | |
Registers and Counter (2/2) | 1. Design of Binary Counters(계속)/ Counters for Other Sequences 2. Counter Design Using S-R and J-K Flip-Flops 3. Derivation of Flip-Flop Input Equations | |
| 7. | |
Analysis of Clocked Sequential Circuit | 1. A Sequential Parity Checker 2. Analysis by Signal Tracing 3. State Table and Graphs/ General Models for Sequential Circuits | |
| 8. | |
Derivation of State Graphs and Tables (1/2) | 1. Design of a Sequence Detector 2. More Complex Design Problems 3. Guidelines for Construction of State Graphs | |
| 9. | |
Derivation of State Graphs and Tables (2/2) | 1. Guidelines for Construction of State Graphs 2. Serial Data Code Conversion 3. Alphanumeric State Graph Notation | |
| 10. | |
Reduction of State Tables State Assignment (1/2) | 1. Elimination of Redundant States/ Equivalent States 2. Determination of State Equivalence Using an Implication Table 3. Equivalent Sequential Circuits | |
| 11. | |
Reduction of State Tables State Assignment (2/2) | 1. Incompletely Specified State Tables/ Derivation of Flip-Flop Input Equations 2. Equivalent State Assignments/ Guidelines for State Assignment 3. Using a One-Hot State Assignment | |
| 12. | |
Sequential Circuit Design (1/2) | 1. Summary of Design Procedure for Sequential Circuits 2. Design Example - Code Converter/ Design of Iterative Circuits 3. Design of Sequential Circuits Using ROMs and PLAs | |
| 13. | |
Sequential Circuit Design (2/2) | 1. Sequential Circuit Design Using CPLDs/ Sequential Circuit Design Using FPGAs 2. Simulation and Testing of Sequential Circuits 3. Overview of Computer-Aided Design | |
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